Design and synthesis of an IEEE-754 exponential function

We have designed a floating-point exponential function using the table-driven method. The algorithm was first implemented using sequential VHDL and later translated to Concurrent Verilog. The main part of the work consisted of creating modules that would handle basic IEEE-754 single-precision number manipulation routines, such as addition, multiplication and rounding to the nearest integer. Using these routines, a model was implemented based on the table-driven algorithm. The VHDL design as well as the Verilog design were estimated, and the results proved to be satisfactory. Synthesis was performed using CMOSIS5 technology on the VHDL code and yielded a fairly large result.