DocumentCode
3345933
Title
Pipelining of parallel multiplexer loops and decision feedback equalizers
Author
Parhi, Keshab K.
Author_Institution
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Volume
5
fYear
2004
fDate
17-21 May 2004
Abstract
The high speed implementation of a DFE (decision feedback equalizer) requires reformulation of the DFE into an array of comparators and a multiplexer loop. The throughput of the DFE is limited by the speed of the multiplexer loop. This paper proposes a novel look-ahead computation approach to pipeline multiplexer loops. The proposed technique is demonstrated and applied to design multiplexer loop based DFEs with throughput in the range of 3.125-10 Gbps.
Keywords
comparators (circuits); decision feedback equalisers; multiplexing equipment; pipeline processing; 3.125 to 10 Gbit/s; comparator array; decision feedback equalizers; high speed DFE implementation; look-ahead computation; parallel multiplexer loops; pipelining; Adaptive filters; CMOS technology; Decision feedback equalizers; Delay; Feedforward systems; Multiplexing; Nonlinear filters; Parallel processing; Pipeline processing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on
ISSN
1520-6149
Print_ISBN
0-7803-8484-9
Type
conf
DOI
10.1109/ICASSP.2004.1327037
Filename
1327037
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