A 256-channel (element) correlator design based on an FPGA for X-ray Photon Correlation Spectroscopy

In this work we have demonstrated a 256-channel(element) correlator array design based on a Virtex 6 FPGA for X-ray Photon Correlation Spectroscopy that uses Dynamic Light Scattering to probe nanometer scale structures, where the channel here means one correlator element which could provide auto correlation functions for 36 lags. This design is incorporated along with a design consisting of a 64×64 pixel silicon detector array and a custom 3D integrated circuit called vertically integrated pixel imaging chip (VIPIC). The challenge was how to handle the large amounts of data from VIPIC while performing correlation analysis in a real time. Our design introduces an autocorrelator per pixel to address the per pixel momentum transfer. Initially the VIPIC collects the X-ray photon arrival events from the 64×64 pixels and transfers it over 16 serial buses to the data acquisition system. Timing information is provided by reading the detector contents every 10μs. Readout can be in one of two modes, a sparsified readout mode for low intensity applications where many pixels acquire no events, and an imaging mode in which all pixels are read out sequentially. The correlator design described here can handle either operating mode. This design provides many advantages over the existing commercial correlators as they are not able to meet the requirements of VIPIC. The commercial ones are limited to low intensity light correlation and a few simultaneous inputs. Besides, the large physical size of the commercial correlators makes the implementation of a system with several channels impractical. A multi-τ correlator design based on virtex 2 was addressed earlier but the practical realization was only ended up for one element of such muti-τ correlator. The correlator design discussed in this paper will provide a correlation dynamic range from 10us to 10.24ms for each of its 256 correlator elements. Our target for the design is to reach the minim- m physical size, resource and power consumption costs based on the approach of using an 8 stage multi-τ design for each element and barrel shift DSPs and pipelined RAM block for the elements. We are planning to implement this design as the basis for a custom integrated circuit which implements 4×256 element correlator elements.