Vertical integration approach to the readout of pixel detectors for vertexing applications

This work is concerned with the design of two different analog channels for hybrid and monolithic pixels readout in view of applications to the SuperB vertex detector. The circuits have been designed in a 130 nm, vertically integrated CMOS technology, which may provide advantages in terms of functional density and electrical isolation between the analog and the digital sections of the front-end. The paper discusses the main features of the two channels, with emphasis on some specific problems and their solution through purposely devised blocks and suitable design criteria. An evaluation of the technology will be also provided through characterization of the prototypes produced within the first 3D multiproject run with Tezzaron/Globalfoundries.