DocumentCode
3346043
Title
Fast carry-look-ahead adder
Author
Raahemifar, Kaamran ; Ahmadi, Majid
Author_Institution
Dept. of Electr. Eng., Windsor Univ., Ont., Canada
Volume
1
fYear
1999
fDate
9-12 May 1999
Firstpage
529
Abstract
This paper presents a high-speed VLSI implementation structure for adder. Innovative serial implementations of carry-look-ahead adders ore developed. The critical path in CLA adders, where the carry is propagated, is implemented using a parallel structure. The supply voltage (V/sub dd/) is 3.9 v which con be lowered to 2.5 v. The adder is in 0.8 /spl mu/m technology. HSPICE simulation shows a total delay of 1.2 ns for 32-bits CLA adder.
Keywords
SPICE; VLSI; adders; carry logic; circuit simulation; delays; high-speed integrated circuits; 0.8 micron; 1.2 ns; 2.5 to 3.3 V; 32 bit; CLA adder; HSPICE simulation; carry-look-ahead adder; high-speed VLSI implementation structure; parallel structure; serial implementations; supply voltage; total delay; Adders; Application software; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Computer applications; Delay; Energy consumption; Equations; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 1999 IEEE Canadian Conference on
Conference_Location
Edmonton, Alberta, Canada
ISSN
0840-7789
Print_ISBN
0-7803-5579-2
Type
conf
DOI
10.1109/CCECE.1999.807254
Filename
807254
Link To Document