A thinning process for an implementation in a pixel array circuit

A thinning process suitable for pixel array circuit implementation is presented. The process is designed to have the computations in parallel and to include only simple logic operations so that the structure of each pixel is simple and the array circuit has an acceptable resolution. Simulation with images of different patterns, including fingerprints, demonstrate that the proposed thinning process is effective, and its results meet the requirement of minutia detection for identification. The structure of such a pixel array circuit is designed as an implementation example and is presented. The circuit has four interconnections per pixel, and can be implemented in a digital CMOS process.