A generalized analog architecture for DCT, DST and its inverse

This paper describes a sampled analog architecture, for computing DCT or DST, using the switched capacitor principle with capacitance switching. The input sample stream is applied to an array of capacitors and multiplied by all the DCT/DST coefficients concurrently using capacitor ratios. These capacitors are switched concurrently with the help of a switching matrix, to realize switched capacitor integrators for performing the necessary addition/subtraction. The architecture may also be used for computing inverse DCT and DST transforms. The proposed architecture is simple, regular and can be used for on-line computations, with good accuracy.