Board level drop test reliability of IC packages

Author

Chai, T.C. ; Quek, Sharon ; Hnin, W.Y. ; Wong, E.H. ; Chia, Julian ; Wang, Y.Y. ; Tan, Y.M. ; Lim, C.T.

Author_Institution

Inst. of Microelectron., Singapore

fYear

2005

fDate

31 May-3 June 2005

Firstpage

630

Abstract

This paper discusses the effect of board design, the failure mechanism and the board level drop impact performance of two types of common IC packages for hand held electronic product applications namely QFN and CSP, when subjected to the JESD22-B111 test methodology. A method to design test board using low cost 2-layer FR4 material instead of more expensive buildup technologies for board level drop impact test have been developed. Finite element analysis (FEA) of the stress and strain fields during drop impact of the CSP and QFN were performed and verified experimentally. In addition, a cyclic constrained bend test has shown good feasibility to be considered as a simpler alternative assessment of solder joint performance under high strain rate loading.

Keywords

chip scale packaging; failure analysis; finite element analysis; impact testing; integrated circuit design; integrated circuit reliability; stress analysis; CSP; FR4; IC packages; JESD22-B111 test methodology; QFN; board design; board level drop test reliability; drop testing; failure mechanism; finite element analysis; strain; stress; Application specific integrated circuits; Capacitive sensors; Chip scale packaging; Design methodology; Electronic equipment testing; Electronics packaging; Failure analysis; Integrated circuit packaging; Integrated circuit testing; Materials testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2005. Proceedings. 55th

ISSN

0569-5503

Print_ISBN

0-7803-8907-7

Type

conf

DOI

10.1109/ECTC.2005.1441335

Filename

1441335