DocumentCode
3347864
Title
A fast low noise CMOS charge sensitive preamplifier for column parallel CCD readout
Author
Walder, J.P. ; Denes, Peter ; Grace, Carl ; Von der Lippe, Henrik ; Zheng, Bob
Author_Institution
Lawrence Berkeley Nat. Lab., Berkeley, CA, USA
fYear
2011
fDate
23-29 Oct. 2011
Firstpage
721
Lastpage
724
Abstract
A fast, low noise charge sensitive preamplifier for column parallel CCD readout application is presented. This prototype has been implemented on a commercial CMOS 65nm process. This preamplifier consists of a two stage transconductance amplifier with capacitive feedback to accommodate two gain ranges and a second transconductance amplifier to reset the circuit. An equivalent noise charge of 37 electrons for a 100ns readout cycle time is achieved for a power consumption of 5mW. Novel design techniques used in this circuit will be presented in detail along with measurement results obtained on the prototype.
Keywords
CMOS analogue integrated circuits; preamplifiers; capacitive feedback; column parallel CCD readout; commercial CMOS 65nm process; equivalent noise charge; fast low noise CMOS charge sensitive preamplifier; power consumption; size 65 nm; stage transconductance amplifier; Linearity;
fLanguage
English
Publisher
ieee
Conference_Titel
Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE
Conference_Location
Valencia
ISSN
1082-3654
Print_ISBN
978-1-4673-0118-3
Type
conf
DOI
10.1109/NSSMIC.2011.6154090
Filename
6154090
Link To Document