Design Models of Pipelined Units for Digital Signal Processing

Author

Hahanova, Iryna ; Miroshnychenko, Yaroslav ; Pobegenko, Irina ; Savvutin, Oleksandr

Author_Institution

DAD Dept., Kharkiv Nat. Univ. of Radio Electron., Kharkiv

fYear

2007

fDate

19-24 Feb. 2007

Firstpage

87

Lastpage

91

Abstract

In this paper the architectural models of pipelined computing units with system-level description, those essentially decrease the design cycle for digital signal processing products, are offered. Practical realization of the filter, that confirms developed design flow effectiveness with software products Simulink (Mathlab) and Active HDL, Aldec Inc., is given.

Keywords

digital signal processing chips; finite state machines; pipeline processing; signal processing; architectural models; design flow; digital image processing; digital signal processing; finite state machine; pipelined computing units; system-level description; Automata; Concurrent computing; Data flow computing; Data processing; Digital images; Digital signal processing; Pipeline processing; Signal design; Signal processing; Signal processing algorithms; digital image processing; digital signal processing; finite state machine; pipelined computing unit;

fLanguage

English

Publisher

ieee

Conference_Titel

CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of

Conference_Location

Lviv-Polyana

Print_ISBN

966-533-587-0

Type

conf

DOI

10.1109/CADSM.2007.4297485

Filename

4297485