DocumentCode
3348163
Title
Exploring last n value prediction
Author
Burtscher, Martin ; Zorn, Benjamin G.
Author_Institution
Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
fYear
1999
fDate
1999
Firstpage
66
Lastpage
76
Abstract
Most load value predictors retain a large number of previously loaded values for making future predictions. In this paper we evaluate the trade-off between tall and slim versus short and wide predictors of the same total size, i.e., between retaining a few values for a large number of load instructions and many values for a proportionately, smaller number of loads. But results show, for example, that even modest predictors holding sixteen kilobytes of values benefit from retaining four values per load instruction when running SPECint95. A detailed comparison of eight load value predictors on a cycle-accurate simulator of a superscalar out-of-order microprocessor shows that our implementation of a last four value predictor outperforms other predictors from the literature, often significantly. With 21 kB of state, it yields a harmonic mean speedup of 12.5% with existing re-fetch misprediction recovery hardware and 13.7% with a not yet realized re-execution recovery mechanism
Keywords
parallel architectures; performance evaluation; SPECint95; cycle-accurate simulator; harmonic mean speedup; last n value prediction; load instructions; load value predictors; superscalar out-of-order microprocessor; Costs; Counting circuits; Delay; Etching; Microprocessors; Out of order; System performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures and Compilation Techniques, 1999. Proceedings. 1999 International Conference on
Conference_Location
Newport Beach, CA
ISSN
1089-795X
Print_ISBN
0-7695-0425-6
Type
conf
DOI
10.1109/PACT.1999.807407
Filename
807407
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