Verification of the Model of Interconnection Capacitances Dependence on Further Neighbourhood in the Bus-Microscopic and Electrical Measurements

Author

Jarosz, A. ; Pfitzner, A.

Author_Institution

Inst. of Electron Technol., Warszawa

fYear

2007

fDate

19-24 Feb. 2007

Firstpage

173

Lastpage

178

Abstract

An analytical model, taking into account the further neighbourhood influence on interconnection capacitances was proposed in our previous works. Previously a test chip designed for the AMS 0.35 mum technology and preliminary results of empirical verification of the model were presented. In this paper complete verification of that model is based on geometrical data obtained with scanning microscopy.

Keywords

VLSI; capacitance; integrated circuit design; integrated circuit interconnections; VLSI circuit design; bus-microscopic measurements; capacitance measurement; electrical measurements; interconnection capacitances; scanning microscopy; size 0.35 micron; Analytical models; Capacitance measurement; Circuit testing; Electric variables measurement; Integrated circuit interconnections; Microscopy; Parasitic capacitance; Semiconductor device measurement; Solid modeling; Very large scale integration; Capacitance Measurement; Interconnection Capacitances Modelling; Verification of VLSI Circuit Design;

fLanguage

English

Publisher

ieee

Conference_Titel

CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of

Conference_Location

Lviv-Polyana

Print_ISBN

966-533-587-0

Type

conf

DOI

10.1109/CADSM.2007.4297516

Filename

4297516