A Vertical Wafer Level Packaging using Through Hole Filled Via Interconnects by Lift Off Polymer Method for MEMS and 3D Stacking Applications

Author

Premachandran, C.S. ; Chong Ser Choong ; Iyer, M.K.

fYear

2005

fDate

31 May-3 June 2005

Firstpage

1094

Lastpage

1098

Keywords

Costs; Filling; Microelectronics; Micromechanical devices; Packaging; Polymers; Silicon; Stacking; Wafer bonding; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2005. Proceedings. 55th

ISSN

0569-5503

Print_ISBN

0-7803-8907-7

Type

DOI

10.1109/ECTC.2005.1441408

Filename

1441408

Link To Document