Title :
A Vertical Wafer Level Packaging using Through Hole Filled Via Interconnects by Lift Off Polymer Method for MEMS and 3D Stacking Applications
Author :
Premachandran, C.S. ; Chong Ser Choong ; Iyer, M.K.
fDate :
31 May-3 June 2005
Keywords :
Costs; Filling; Microelectronics; Micromechanical devices; Packaging; Polymers; Silicon; Stacking; Wafer bonding; Wafer scale integration;
Conference_Titel :
Electronic Components and Technology Conference, 2005. Proceedings. 55th
Print_ISBN :
0-7803-8907-7
DOI :
10.1109/ECTC.2005.1441408
