Performance Evaluation of Cluster-Based Homogeneous Multiprocessor System-on-Chip Using FPGA Device

Author

Geng Luo-Feng ; Zhang Duo-Li ; Gao Ming-Lun

Author_Institution

Inst. of VLSI Design, Hefei Univ. of Technolgoy, Hefei, China

fYear

2009

fDate

10-12 Dec. 2009

Firstpage

1

Lastpage

4

Abstract

The cluster-based multiprocessor system-on-chip (MPSoC), which adopts the hybrid interconnection composed of both bus-based and NoC architecture, is a new infrastructure for MPSoC. For obtaining the fast exploration of multiple hardware (HW) and software (SW) implementation alternatives with accurate estimations of performance to tune the MPSoC architecture in an early stage of the design process, this paper use the FPGA device to prototype the cluster-based MPSoC with 17 processing cores. And, a suite of benchmarks, including several parallel applications with different characteristic of parallelism, workload and communication pattern, are designed and presented in this paper. The experiment results show that, the highest speed up ratio is up to 15.850.

Keywords

field programmable gate arrays; interconnections; system-on-chip; FPGA device; MPSoC architecture; NoC architecture; bus-based architecture; cluster-based homogeneous multiprocessor system-on-chip; field programmable gate arrays; hybrid interconnection; Application software; Computer architecture; Field programmable gate arrays; Hardware; Multiprocessing systems; Network-on-a-chip; Parallel processing; Prototypes; Software performance; Software prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Embedded and Multimedia Computing, 2009. EM-Com 2009. 4th International Conference on

Conference_Location

Jeju

Print_ISBN

978-1-4244-4995-8

Type

conf

DOI

10.1109/EM-COM.2009.5402984

Filename

5402984