Power-Aware Mapping for Network-on-Chip Architectures under Bandwidth and Latency Constraints

This paper investigates the bandwidth- and latencyconstrained IP mapping problem that maps a given set of IP cores onto the tiles of a mesh-based Network-on-Chip (NoC) architecture to minimize the power consumption due to intercore communications. By examining various applications´ communication characteristics shown in their communication trace graphs, two distinguishable connectivity templates are realized: the graphs with tightly coupled vertices and those with distributed vertices. Different mapping heuristics are developed for these templates: tightly coupled vertices are mapped onto tiles that are close to each other while the distributed vertices are mapped following a graph partition scheme. The proposed template-based mapping algorithm achieves on average 15% power saving compared with MOCA, a fast greedy-based algorithm. Compared with a branch-and-bound algorithm, the proposed algorithm can generate results of almost the same quality but require much less CPU time.