DocumentCode
3348624
Title
Checking and Reconfiguration Techniques for Multi-version IIP in SoPC
Author
Prokhorova, Julia
Author_Institution
Comput. Syst. & Networks Dept., Nat. Aerosp. Univ., Kharkov
fYear
2007
fDate
19-24 Feb. 2007
Firstpage
192
Lastpage
193
Abstract
The different techniques of checking and reconfiguration for fault-tolerant system-on-programmable-chip (SoPC) based on FPGA projects are proposed. To develop SoPC the redundant infrastructure intellectual property (IIP) is used. The feature of proposed FPGA IIP is application of multi-version IPs to ensure systems tolerance to physical and design faults.
Keywords
field programmable gate arrays; industrial property; system-on-chip; FPGA; SoPC; fault tolerance; infrastructure intellectual property; reconfiguration; system-on- programmable-chip; Bellows; Conferences; Data communication; Fault tolerant systems; Field programmable gate arrays; Intellectual property; Paper technology; Power system reliability; Testing; Wireless sensor networks; Fault-tolerance; Infrastructure IP cores; Multiversity; System-on-Programmable-Chip;
fLanguage
English
Publisher
ieee
Conference_Titel
CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of
Conference_Location
Lviv-Polyana
Print_ISBN
966-533-587-0
Type
conf
DOI
10.1109/CADSM.2007.4297522
Filename
4297522
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