PRESSNoC: Power-Aware and Reliable Encoding Schemes Supported Reconfigurable Network-on-Chip Architecture

We propose a Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) architecture whereby an encoding can be selected by a REasoning And Learning (REAL) framework at run-time to fit the reliability and power requirements of the application and its execution environment. PRESSNoC was implemented on a Xilinx Virtex 4 FPGA device, which required 25.5% lesser number of slices compared to the traditional NoC with a full-fledged encoding method. The average benefit to overhead ratio of the proposed architecture is greater than that of the traditional architecture by 71%, 32%, and 277% when we consider the individual effects of interference rate per instruction, application domains, and system characteristics, respectively. It shows we have higher probability toward the reduction of crosstalk interferences and dynamic power consumption at the same overheads by using the proposed architecture.