A Loop-Improved Capacitor-Less Low-Dropout Regulator for SoC Power Management Application

Stability is the major obstacle for capacitor-less low- dropout regulator (LDO). By using Miller compensation, a low frequency dominant pole is internally generated, and two other non-dominant poles, which frequency are higher than unity gain frequency (UGF), can be configured by Damping-Factor-Control (DFC) block. With opposed zero cancellation, single pole system is formed before UGF and satisfied phase margin is achieved, hence both the system stability and optimized transient performance are ensured. Based on DFCFC, a 1.8V 100 mA capacitor-less LDO was designed by using HHNEC 0.25 mum standard CMOS process in this paper. Simulation results showed that the improved regulator could provide a full load transient response of 2 mus settling time and both overshoots and undershoots less than 70 mV. Furthermore, 50 mV dropout voltage, 40 muA quiescent current, and smaller compensation capacitors cater to low power and low cost SoC application.