A Framework for the Correction of Multi-Bit Errors in Multi-Core Processors

With the development of the scaling technologies, it´s more susceptible to the transient faults for the modern microprocessors, so the error-correcting codes are used to detect and correct the errors in caches. In this paper, an enhanced architecture is proposed for the selective use of strong multi-bit ECC, where the main character is the extended L2 core, protected by Hamming distance to detect errors, and carried some redundancy-based schemes to correct errors. To the detailed design of the cache, these schemes includes the L1/L2 cache redundancy, fine grain dirtiness, reliability-centric replacement and the methods to exploit small data value size.