High-Speed Method of Hardware Simulation

Author

Hahanov, Vladimir ; Kamenuka, Eugeniy ; Kteiman, Hassan ; Ghribi, Wade ; Radivilova, Tamara

Author_Institution

DAD Dept., Kharkov Nat. Univ. of Radio Electron., Kharkov

fYear

2007

fDate

19-24 Feb. 2007

Firstpage

222

Lastpage

225

Abstract

Hardware implementation of triadic fault-free simulation method HES-MV - hardware embedded simulation based on multi-valued alphabet is proposed. This method uses hardware gate and RTL models for large scale digital designs description. Structure solutions for logic elements models implementation are presented. Logic element has two bits for four values encoding for each input or output line of simulated device.

Keywords

hardware description languages; large scale integration; logic design; logic simulation; RTL models; VHDL language; hardware embedded simulation; hardware gate; hardware implementation; high-speed method; large scale digital design; logic elements model; multivalued alphabet; structure solutions; triadic fault-free simulation method; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Discrete event simulation; Electronic design automation and methodology; Hardware; Large-scale systems; Logic devices; System testing; HES technology; Software/hardware implementation; simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of

Conference_Location

Lviv-Polyana

Print_ISBN

966-533-587-0

Type

conf

DOI

10.1109/CADSM.2007.4297530

Filename

4297530