DocumentCode :
3348940
Title :
Verification Challenges of NoC Architectures
Author :
Hahanov, Vladimir ; Yegorov, Oleksandr ; Mostova, Karyna ; Kovalyov, Eugene
Author_Institution :
Dept. of DAD, Kharkov Nat. Univ. of Radio Electron., Kharkov
fYear :
2007
fDate :
19-24 Feb. 2007
Firstpage :
266
Lastpage :
269
Abstract :
In this paper different approaches of NoC design, main concepts and popular NoC architectures and verification challenges of NoC design are described.
Keywords :
logic design; logic testing; network-on-chip; NoC design; NoC verification; network-on-chip architecture; Network-on-a-chip; Network-on-chip; NoC verification; OCP;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of
Conference_Location :
Lviv-Polyana
Print_ISBN :
966-533-587-0
Type :
conf
DOI :
10.1109/CADSM.2007.4297543
Filename :
4297543
Link To Document :
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