An accurate and efficient performance analysis technique for multiprocessor snooping cache-consistency protocols

A family of dynamic cache-consistency-protocols for shared-bus multiprocessor systems is considered. A modeling approach, based on the specification and the iterative solution of sets of equations that express the mean values of interesting performance measures in terms of the mean values of certain model inputs, is presented. The equations are intuitive, in the sense that each can be explained simply in terms of the mechanics of the architecture being modeled. The solution technique is extremely efficient, requiring on the order of one second of CPU time for systems of arbitrary size. This makes it possible to explore a large design space quickly and interactively. The results are essentially as accurate as those of the previously existing techniques, which took hours on I-MIPS processors