DocumentCode :
3349067
Title :
Models of Circuits and Their Elements for Functional Decomposition and Verification at the Stage of Computer Systems´ PC Boards Design
Author :
Al-Zabi, Bilal ; Kernytskyy, Andriy ; Tkatchenko, Sergiy
Author_Institution :
CAD/CAM Dept., Lviv Polytech. Nat. Univ., Lviv
fYear :
2007
fDate :
19-24 Feb. 2007
Firstpage :
286
Lastpage :
287
Abstract :
The possibilities of application of theoretical and graph models of circuits when solving tasks of optimization and verification in planning of the computer systems are considered. The use of the nets weighed at vertexes is offered.
Keywords :
circuit layout CAD; circuit optimisation; formal verification; graph theory; printed circuit layout; printed circuit testing; circuit models; circuit optimization; computer systems´ PC boards design; functional lay-decomposition; graph models; Application software; CADCAM; Circuit topology; Computer aided manufacturing; Design optimization; Graph theory; Heuristic algorithms; Polynomials; Programming; Set theory; circuit; computer systems; functional verification; graphs;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of
Conference_Location :
Lviv-Polyana
Print_ISBN :
966-533-587-0
Type :
conf
DOI :
10.1109/CADSM.2007.4297552
Filename :
4297552
Link To Document :
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