DocumentCode :
3349323
Title :
Using MMAP for mixed signal empirical substrate design optimization
Author :
Robertson, Glenn
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fYear :
2005
fDate :
31 May-3 June 2005
Firstpage :
1383
Abstract :
Mixed signal and RF package development with each generation continues in complexity with continued process evolution and smaller more dense packages. BGA packages have decreased in ball pitch where 0.5 mm pitch is becoming common. Trace pitch on substrates are found in many products to 25μm. As dimensions scale the difficulties with noise and impedance control and variance become greater. Increased interconnect densities with future silicon technologies increase at a faster rate than package substrate interconnect density. With cost and footprint size a major consideration in the development of new mixed signal and RF products, the use and availability from suppliers of CSP (chip scale packaging) on MMAP (molded matrix array packaging) technology is increasing. In using substrate layout design ´flavors´ in a single MMAP strip, we have been able to determine best substrate design performance for mixed signal LAN and RF products. For the Ethernet LAN product we were able to match performance on a BGA package to the same die in a lead frame package. For the RF product, we were able to provide the proper inductance to operate in the correct frequency for test. The empirical performance data from the substrate experiment validated both the substrate design and the correct substrate layout approach to support a final substrate (full strip) design. We were able to show optimal performance results in minimum development time. How the multiple substrate design flavors are implemented on a MMAP strip and the results obtained is discussed. Additionally the ´flavors´ design was used to improve flip chip product reliability by allowing testing of various copper densities in a flip chip package to prevent bump delamination.
Keywords :
ball grid arrays; chip scale packaging; circuit optimisation; flip-chip devices; integrated circuit design; integrated circuit interconnections; mixed analogue-digital integrated circuits; 0.5 mm; Ethernet LAN; RF package development; ball grid array package; chip scale packaging; copper density; flip chip product reliability; impedance control; interconnect density; mixed signal LAN; mixed signal empirical substrate design optimization; mixed signal package development; molded matrix array packaging; noise control; silicon technology; substrate layout design flavors; trace pitch; Chip scale packaging; Design optimization; Flip chip; Local area networks; RF signals; Radio frequency; Signal design; Signal processing; Strips; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2005. Proceedings. 55th
ISSN :
0569-5503
Print_ISBN :
0-7803-8907-7
Type :
conf
DOI :
10.1109/ECTC.2005.1441450
Filename :
1441450
Link To Document :
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