Interface Design for Hardware-in-the-Loop Simulation

This paper presents a scalable approach to interface between a time-triggered distributed hardware-in-the-loop (HIL) simulator and the system under test (SUT) via smart virtual transducers (SVTs). An SVT is an element of an HIL simulator and implements two interfaces - a standardized digital interface to a time-triggered transducer network and a transducer-specific interface. The main contribution of the approach is a separation of the execution of the simulation model and the deterministic interaction via an arbitrary transducer interface. The benefit of such separation is the temporal decoupling between simulation model execution and interaction with the SUT. Furthermore, the approach leads to a reduction of complexity of the simulation setup. The application of the approach is shown by an SVT prototype that is used to simulate a temperature sensor