A graph theoretic approach to the clock distribution problem

Global electrical design issues such as power distribution and clock distribution in ASIC design have assumed added dimensions as feature sizes below one micron and device counts of more than a million are becoming feasible. The authors present a methodology for optimally distributing the clock signal in synchronous digital VLSI circuits. Optimality is measured in terms of minimizing delay in each critical path as well as the differences in delays between different paths. The inputs to the system consist of the location of each cell, the input capacitance of each cell and the locations of all possible buffer sites. The outputs consist of the optimal number and location of buffers as well as a netlist for routing the clock signal. This system provides an application specific methodology for optimal clock distribution whose utility increases with the size of the circuit