Issues in designing high-frequency systems with ASICs

Submicron ASIC technology and high-frequency devices place different demands on the CAE/CAD environment. As device geometries shrink, secondary electronic effects, such as fan-out, slew rate, transmission-line effects and noise take on considerably more importance. These requirements impose new demands on the ASIC design process. To properly address the needs of high speed ASIC designs, simulation and system level tools need to be brought closer together to form a homogeneous design environment. An environment where concurrent optimization of the various design criterias are facilitated and encouraged. Key to the success of such an environment is sophisticated point tools, as well as a proven framework technology that allows efficient communication and data sharing among tools. Valid Logic Systems offers such an environment where state-of-the-art design capture tools are integrated with advanced simulation and physical design tools through the application of ValidFrame technology