Title :
An ASIC level BIST implementation for system level testing
Author :
Stroud, Charles E. ; Shaw, Robert F.
Author_Institution :
AT&T Bell Labs., Naperville, IL, USA
Abstract :
The architecture and operation of a built-in self-test (BIST) implementation at the ASIC level for use at manufacturing unit level testing and system diagnostics is described. Analysis of this BIST approach is given in terms of area overhead, fault coverage, reduction in manufacturing testing costs, and reduction in system diagnostic execution time
Keywords :
application specific integrated circuits; built-in self test; digital integrated circuits; integrated circuit testing; production testing; ASIC level; BIST implementation; area overhead; built-in self-test; fault coverage; manufacturing unit level testing; system diagnostics; system level testing; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Compaction; Hardware; Manufacturing; Registers; Software testing; System testing;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242852
