Title :
Explicit elimination of easy-to-test faults in a sequential test generator
Author :
Ku, Tsu-Wei ; Chia, Wei-Kong
Author_Institution :
Hitachi Micro Syst. Inc., San Jose, CA, USA
Abstract :
The authors describe how to eliminate easy-to-test faults after each sequential test vector is generated. The elimination process is conducted using a combinational test generator. Two new classes of faults called 0-step and 1-step testable faults are defined. The percentages of such faults are determined for MCNC benchmark circuits. The CPU time can be up to 150% faster than STEED (a Berkley sequential test generator) and the number of test vectors can be 38% less
Keywords :
logic testing; sequential circuits; CPU time; MCNC benchmark circuits; elimination process; sequential test generator; test vectors; Benchmark testing; Central Processing Unit; Circuit faults; Circuit testing; Fault detection; Logic arrays; Logic testing; Redundancy; Sequential analysis; Sequential circuits;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242854
