DocumentCode
3349700
Title
A fault tolerant approach to microprocessor design
Author
Weaver, Chris ; Austin, Todd
Author_Institution
Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
fYear
2001
fDate
1-4 July 2001
Firstpage
411
Lastpage
420
Abstract
We propose a fault-tolerant approach to reliable microprocessor design. Our approach, based on the use of an online checker component in the processor pipeline, provides significant resistance to core processor design errors and operational faults such as supply voltage noise and energetic particle strikes. We show through cycle-accurate simulation and timing analysis of a physical checker design that our approach preserves system performance while keeping area overheads and power demands low. Furthermore, analyses suggest that the checker is a fairly simple state machine that can be formally verified, scaled in performance, and reused. Further simulation analyses show virtually no performance impacts when our simple checker design is coupled with a high-performance microprocessor model. Timing analyses indicate that a fully synthesized unpipelined 4-wide checker component in 0.25 μm technology is capable of checking Alpha instructions at 288 MHz. Physical analyses also confirm that costs are quite modest; our prototype checker requires less than 6% the area and 1.5% the power of an Alpha 21264 processor in the same technology. Additional improvements to the checker component are described which allow for improved detection of design, fabrication and operational faults.
Keywords
computer architecture; fault tolerant computing; finite state machines; instruction sets; microprocessor chips; performance evaluation; 0.25 mum; Alpha 21264 processor; Alpha instructions; area overheads; core processor design errors; cycle-accurate simulation; energetic particle strikes; fault tolerant approach; fully synthesized unpipelined 4-wide checker component; high-performance microprocessor model; online checker component; operational faults; physical checker design; power demands; processor pipeline; prototype checker; reliable microprocessor design; simple checker design; simple state machine; supply voltage noise; system performance; timing analyses; timing analysis; Analytical models; Fault tolerance; Microprocessors; Performance analysis; Pipelines; Power demand; Process design; System performance; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Dependable Systems and Networks, 2001. DSN 2001. International Conference on
Conference_Location
Goteborg, Sweden
Print_ISBN
0-7695-1101-5
Type
conf
DOI
10.1109/DSN.2001.941425
Filename
941425
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