Finite state machine optimization algorithms for pipelined data path controllers

Author

Kim, James Jongtae ; Kurdahi, Fadi J.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38169

Abstract

Algorithms for generating an optimal finite state machine (FSM) implementation of pipelined data path controllers are presented. The groups of states are partitioned into two, states are encoded, and each partition is mapped onto one PLA to form a two-PLA based Moore-style FSM state sequencer. The experimental results show that substantial savings in layout area can be achieved compared to published traditional FSM optimization approaches

Keywords

circuit layout CAD; finite state machines; logic CAD; logic arrays; optimisation; pipeline processing; FSM state sequencer; Moore-style; PLA; layout area; optimization algorithms; pipelined data path controllers; Automata; Circuit synthesis; Combinational circuits; Data engineering; Data flow computing; Flow graphs; Optimal control; Pipeline processing; Programmable logic arrays; Resource management;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242867

Filename

242867

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3349871