• DocumentCode
    3350101
  • Title

    Thermo-mechanical analysis for a multi chip build up substrate based package

  • Author

    Zhang, Xiaowu ; Lee, Charles ; Hua, Wong Ee ; Iyer, Mahadevan K. ; Siong, Teo Poi ; Pinjala, Damaruganath ; Srinivasamurthy, S.

  • Author_Institution
    Inst. of Microelectron., Singapore
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    67
  • Lastpage
    72
  • Abstract
    This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the 2nd level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. Firstly, the effect of the positioning of four silicon dice within the MCM package on the package warpage was studied. Secondly, the effect of package dimensions (the heat spreader thickness, structural adhesive thickness and substrate thickness) on the maximum residual stress and warpage of the package were performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of the solder joints is estimated by Darveaux´s approach. A series of parametric studies is performed by changing the package dimensions. The results obtained from the modeling are useful for the design of multichip packages
  • Keywords
    adhesives; circuit analysis computing; circuit reliability; creep; deformation; fatigue; finite element analysis; flip-chip devices; heat sinks; integrated circuit interconnections; integrated circuit packaging; laminates; microassembling; multichip modules; soldering; thermal stresses; 3D sliced model; Darveaux´s method; MCM assembly; MCM package; MCM package design; Si die positioning; Sn-Pb solder; SnPb; build up substrate; creep constitutive relation; fatigue life; finite element model; flip chips; heat spreader thickness; maximum residual stress; modeling; multi chip build up substrate based package; multichip module package design; multichip package design; package dimensions; package warpage; second level solder joint reliability; solder joint reliability; solder joints; structural adhesive thickness; substrate thickness; temperature dependence; thermal cycling; thermally induced stress; thermo-mechanical analysis; time dependence; warpage; Assembly; Creep; Flip chip; Multichip modules; Packaging; Residual stresses; Silicon; Soldering; Thermal stresses; Thermomechanical processes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on the
  • Print_ISBN
    0-7803-6675-1
  • Type

    conf

  • DOI
    10.1109/IPFA.2001.941457
  • Filename
    941457