DocumentCode
3350132
Title
PLD implements cache control for a 33-MHz 80486
Author
Legenhausen, Jay
Author_Institution
Cypress Semiconductor, San Jose, CA, USA
fYear
1991
fDate
23-27 Sep 1991
Lastpage
38018
Abstract
A no-wait-state, 33-MHz, 486 second-level cache controller, which usually requires a custom ASIC, has been implemented in a single PLD. The complexity of the design typifies what can be fit into current high-density PLDs for high-speed applications. A description of the design illustrates the necessary design techniques for this application
Keywords
PLD programming; buffer storage; logic arrays; storage management chips; 33 MHz; 80486; 80486 second cache controller; PLD implemented cache control; clock 33 MHz; design techniques; high-density PLDs; high-speed applications; second-level cache controller; single PLD; Application specific integrated circuits; Automatic control; Random access memory; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242883
Filename
242883
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