ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

ESD robustness of CMOS devices used in the I/O pad is a major reliability issue as the diffusion junction depth is reduced and LDD (lightly-doped drain)/salicide structures are generally used in sub-quarter-micron CMOS technology. In order to enhance ESD robustness, some ESD implantations have been reported for inclusion into the process flow to modify the device structures for ESD protection (Lee, 1997; Hsue and Ko, 1994; Lowrey and Chance, 1996; Yang, 2000). In this paper, the effectiveness of different ESD implantation solutions on NMOS and diode devices for ESD protection is investigated in a 0.18 μm salicided bulk CMOS process. The second breakdown current (It2) of the fabricated devices is measured by the transmission line pulse generator (TLPG). The human-body-model (HBM) and the machine-model (MM) ESD levels of these devices are also measured and compared. The layout dependence of NMOS devices and diodes with different ESD implantations are also investigated