DocumentCode :
3350191
Title :
Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process
Author :
Ker, Ming-Dou ; Hung, Kei-Kang ; Tang, Howard T H ; Huang, S.-C. ; Chen, S.S. ; Wang, M.-C.
Author_Institution :
Integrated Circuits & Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2001
fDate :
2001
Firstpage :
91
Lastpage :
96
Abstract :
Due to the low thermal conductivity of the buried oxide underneath the thin-film silicon layer and the shallow-trench-isolation (STI) structure on the insulating layer, electrostatic discharge (ESD) robustness of CMOS devices in silicon-on-insulator (SOI) CMOS technology has become a major reliability challenge (Chan et al., 1994; Raha et al., 1999; Smith, 1998). As SOI technology continues to be scaled down, the thickness of the top layer silicon film is decreased, and the junction area for ESD protection devices to discharge ESD current becomes smaller. Therefore, the ability to dissipate the heat generated by ESD events in SOI CMOS ICs is seriously degraded. In this paper, two novel diode structures with effective larger p-n junction area for better heat dissipation in partially-depleted SOI CMOS technology are proposed. The I-V characteristics and ESD robustness of these new diodes are investigated and compared to that of the Lubistor diode (Voldman et al., 1996)
Keywords :
CMOS integrated circuits; buried layers; cooling; electric current; electrostatic discharge; integrated circuit reliability; integrated circuit testing; isolation technology; protection; semiconductor diodes; silicon-on-insulator; thermal conductivity; thermal management (packaging); 0.15 micron; 1.8 V; CMOS devices; ESD current discharge; ESD events; ESD protection circuits; ESD protection devices; ESD robustness; I-V characteristics; Lubistor diode; SOI CMOS ICs; SOI CMOS technology; SOI technology scaling; STI structure; Si-SiO2; buried oxide; diode structures; diodes; electrostatic discharge robustness; heat dissipation; heat generation; insulating layer; junction area; p-n junction area; partially-depleted SOI CMOS technology; partially-depleted SOI salicided CMOS process; reliability; shallow-trench-isolation structure; silicon-on-insulator CMOS technology; thermal conductivity; thin-film silicon layer; top layer silicon film thickness; CMOS technology; Diodes; Electrostatic discharge; Protection; Robustness; Semiconductor thin films; Silicon on insulator technology; Thermal conductivity; Thin film circuits; Thin film devices;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on the
Print_ISBN :
0-7803-6675-1
Type :
conf
DOI :
10.1109/IPFA.2001.941462
Filename :
941462
Link To Document :
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