Clock layout for high-performance ASIC based on weighted center algorithm

A new clock distribution scheme is investigated using weighted center algorithm. The algorithm is based on optimum matching of the closest clock terminals and recursively building a clock tree which connects all the clock terminals. The novel feature of the authors´ approach is simultaneous minimizing of the clock skew and the total clock tree wire length, and suitable for any design style. Experimental results on the MCNC industrial benchmarks show that this approach is practical and promising