A high level simulator feasible for reliability analysis of VLSI circuits

Author

Chung, Steve S. ; Chang, T.-S. ; Hsu, P.-C.

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38018

Abstract

A high level timing simulator has been developed with emphasis on design-for-reliability of VLSI circuits, in particular digital circuits. It features high speed performance which is at least 100× faster than SPICE for circuit simulation. The input is at the gate-level and so is more suitable for VLSI circuit analysis. A new reliability model is also incorporated in the simulator so that the simulator is feasible for reliability analysis of device or circuit degradation due to the hot carrier effect. Two typical examples for predicting the lifetime of a device or circuit in a VLSI environment are demonstrated

Keywords

VLSI; circuit analysis computing; hot carriers; insulated gate field effect transistors; reliability; semiconductor device models; VLSI circuit analysis; VLSI circuits; circuit degradation; circuit simulation; design-for-reliability; device degradation; device lifetime prediction; digital circuits; feasible for reliability analysis; high level timing simulator; high speed performance; hot carrier effect; reliability model; Analytical models; Circuit analysis; Circuit simulation; Degradation; Equations; Hot carriers; SPICE; Stress; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242889

Filename

242889