Memorist: a diffused CMOS SRAM compiler for gate array applications

Author

Tou, Jarvis ; Gee, Perry ; Duh, John ; Eesley, Rick

Author_Institution

ASIC Div., Motorola Inc., Chandler, AZ, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38565

Abstract

A flexible SRAM compiler has been developed to generate high speed, high density, synchronous CMOS memories. The fully diffused single and dual port designs allow for a high level of memory integration into a gate array environment targeted for system solutions. The compiler provides for accurate multi-level timing characterization and is tightly integrated into an ASIC development system. A 4-die test-chip cluster has been developed

Keywords

CMOS integrated circuits; SRAM chips; VLSI; application specific integrated circuits; circuit layout CAD; logic arrays; 4-die test-chip cluster; ASIC development system; Memorist; diffused CMOS SRAM compiler; flexible SRAM compiler; gate array applications; gate array environment; memory integration; multi-level timing characterization; synchronous CMOS memories; Application specific integrated circuits; CMOS technology; Delay; Graphics; Packaging; Random access memory; Read-write memory; Synchronous generators; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242891

Filename

242891

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3350273