Solder joint fatigue and reliability of chip scale packages: a failure analysis strategy

Author

Mohamed, Shamsul ; Francis, Caroline ; Yew, Lam Boon ; Mun, Tang Wye ; Ki, Lim Too

Author_Institution

Adv. Micro Devices, Penang, Malaysia

fYear

2001

fDate

2001

Firstpage

142

Lastpage

145

Abstract

This paper outlines an optimal approach for board level chip scale package (CSP) failure analysis, where the chip and printed circuit board (PCB) are analyzed as a single unit. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was specifically developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions on both package and PCB, substrate warpage, heating profiles/reflow, intermetallic compound (IMC) thickness and solder joint voids

Keywords

chip scale packaging; circuit reliability; deformation; failure analysis; fatigue; printed circuit testing; reflow soldering; temperature distribution; voids (solid); CSP pad dimensions; IMC thickness; PCB; PCB pad dimensions; board level CSP failure analysis; chip scale packages; cross-section; failure analysis strategy; heating profiles; intermetallic compound thickness; parallel polishing; printed circuit board; solder joint fatigue; solder joint height; solder joint reliability; solder joint voids; substrate warpage; Assembly; Bonding; Chip scale packaging; Failure analysis; Fatigue; Heating; Inspection; Printed circuits; Soldering; Transmission line matrix methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on the

Print_ISBN

0-7803-6675-1

Type

conf

DOI

10.1109/IPFA.2001.941473

Filename

941473