Borderless contact leakage induced standby current failure on sub-0.15 μm CMOS device

For the downscaling of CMOS device design rules with high device performance, the reduced active area forces formation of a borderless contact in local interconnects. As the contact area is decreased with downscaling, it induces failure of device electrical characteristics and reliability. The ultra-shallow junction structures used as basic technology for sub-0.15 μm CMOS devices and the junction leakage induced by borderless contact leakage at the shallow trench edge are serious problems for CMOS devices with low standby power dissipation. Recently, several borderless contact structures have been reported (Gallagher et al., 1995; Subbanna et al., 1993; Wen-Chau Liu et al., 2000). In this paper, we estimate the electrical characteristics of borderless contact and demonstrate the borderless contact leakage induced standby failure on a sub-0.15 μm 6-Tr SRAM device