• DocumentCode
    3350537
  • Title

    Predicated static single assignment

  • Author

    Carter, Lemuria ; Simon, Bernd ; Calder, Brian ; Carter, Lemuria ; Ferrante, J.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    245
  • Lastpage
    255
  • Abstract
    Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural mechanism that increases instruction level parallelism by removing branches and allowing simultaneous execution of multiple paths of control, only committing instructions from the correct path. In order for the compiler to expose such parallelism, traditional compiler data-flow analysis needs to be extended to predicated code. In this paper we present predicated static single assignment (PSSA) to enable aggressive predicated optimization and instruction scheduling. PSSA removes false dependences by exploiting renaming and information about the multiple control paths. We demonstrate the usefulness of PSSA for predicated speculation and control height reduction. These two predicated code optimizations used during instruction scheduling reduce the dependence length of the critical paths through a predicated region. Our results show that using PSSA to enable speculation and control height reduction reduces execution time from 10% to 58%
  • Keywords
    data flow analysis; parallel architectures; processor scheduling; program compilers; aggressive predicated optimization; architectural mechanism; branch removal; compiler data-flow analysis; critical paths; dependence length; false dependency reduction; instruction level parallelism; instruction scheduling; multiple control paths; predicated execution; predicated static single assignment; renaming; simultaneous multiple control path execution; wide issue architectures; Computer aided instruction; Computer architecture; Computer science; Concurrent computing; Data analysis; Flow graphs; VLIW;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures and Compilation Techniques, 1999. Proceedings. 1999 International Conference on
  • Conference_Location
    Newport Beach, CA
  • ISSN
    1089-795X
  • Print_ISBN
    0-7695-0425-6
  • Type

    conf

  • DOI
    10.1109/PACT.1999.807561
  • Filename
    807561