DocumentCode :
3350586
Title :
Plasma process-induced latent damage on gate oxide-demonstrated by single-layer and multi-layer antenna structures
Author :
Wang, Zhichun ; Ackaert, Jan ; Salm, Cora ; Kuper, Fred
Author_Institution :
MESA Res. Inst., Twente Univ., Enschede, Netherlands
fYear :
2001
fDate :
2001
Firstpage :
220
Lastpage :
223
Abstract :
In this paper, by using both single-layer (SL) and multi-layer (ML) or stacked antenna structures, a simple experimental method is proposed to directly demonstrate the pure plasma process-induced latent damage on gate oxide without any impact of additional defects generated by normal constant current stress (CCS) revealing technique. The presented results show that this method is effective for study of the latent damage
Keywords :
CMOS integrated circuits; dielectric thin films; integrated circuit reliability; integrated circuit testing; plasma materials processing; surface treatment; CMOS back-end-of-line process; SiO2-Si; constant current stress defects; constant current stress revealing technique; gate oxide; latent damage; multi-layer antenna structures; plasma process-induced latent damage; single-layer antenna structures; stacked antenna structures; Carbon capture and storage; Electron traps; Plasma applications; Plasma devices; Plasma materials processing; Plasma properties; Protection; Stress; Testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on the
Print_ISBN :
0-7803-6675-1
Type :
conf
DOI :
10.1109/IPFA.2001.941490
Filename :
941490
Link To Document :
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