A vertically integrated test methodology based on JTAG IEEE 1149.1 Standard Interface

A vertically integrated test methodology has been developed for ASIC testing based on the IEEE 1149.1 Standard Test Interface. A common interface is used to test at the wafer, packaged-chip and board/system levels. The boundary scan JTAG interface is combined with an internal full scan based test technique to provide a uniform test procedure at all stages of testing. At the prototype debug phase, the test circuitry is configured to test for design and process faults. At the manufacturing stage, it allows for efficient wafer sorting and packaged chip testing. At the board/system level, the same test set used at the wafer and package levels can be employed for incoming-inspection of parts and in-circuit-testing. In addition to basic scan testing, the protocol can perform AC/delay-fault testing. For embedded megacell and RAM module testing it is configured to control and operate an independent BIST scheme inside the ASIC device to achieve at-speed testing. This test methodology has been implemented on practical ASIC parts. The area overhead for the boundary scan architecture is on the order of a few percent for 30-50 K gate designs, and depending on the type of implementation, performance overhead varies from minimal to no penalty at the I/O cells