Stress-induced leakage current in thin oxides under high-field impulse stressing

Author

Tan, Y.N. ; Chim, W.K. ; Lim, P.S.

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore

fYear

2001

fDate

2001

Firstpage

228

Lastpage

233

Abstract

Stress-induced leakage current (SILC) decreases when the time-between-pulses (T_bp) of an AC-pulse waveform is increased. The amount of SILC reduction generally decreases for the same increase in T_bp, with increasing stress voltage magnitude and stress pulse width. A model developed to describe the trap generation and relaxation processes occurring during transient high-field stress from unipolar and bipolar pulse waveforms is presented in this paper

Keywords

EPROM; MOS capacitors; MOS memory circuits; dielectric thin films; electron traps; high field effects; hole traps; impulse testing; integrated circuit modelling; integrated circuit testing; leakage currents; AC-pulse waveform; EEPROM; MOS capacitors; SILC; SILC reduction; SiO₂-Si; bipolar pulse waveforms; high-field impulse stressing; relaxation processes; stress pulse width; stress voltage magnitude; stress-induced leakage current; thin oxides; time-between-pulses; transient high-field stress; trap generation; unipolar pulse waveforms; Failure analysis; Integrated circuit reliability; Leakage current; MOS capacitors; Pulse generation; Space vector pulse width modulation; Stress; Substrates; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on the

Print_ISBN

0-7803-6675-1

Type

conf

DOI

10.1109/IPFA.2001.941492

Filename

941492