Title :
Toshiba IEEE 1149.1 (JTAG) development summary
Author_Institution :
Toshiba America Electronic Components Inc., Sunnyvale, CA, USA
Abstract :
TAEC has developed a simple and versatile IEEE 1149.1 (JTAG) sub-system methodology for high performance gate array ASICs based on a modular scheme with sub-nanosecond propagation delay penalties for CMOS I/O voltage levels. The scheme uses 14 different macrofunctions which can be combined to form a variety of JTAG sub-systems
Keywords :
CMOS integrated circuits; application specific integrated circuits; boundary scan testing; integrated circuit testing; logic arrays; logic testing; CMOS I/O voltage levels; IEEE 1149.1 subsystem methodology; JTAG architecture; Toshiba; gate array ASICs; modular scheme; propagation delay penalties; soft macrofunctions; Application specific integrated circuits; CMOS technology; Circuit testing; Clocks; Electronic components; Instruction sets; Macrocell networks; Pins; Propagation delay; Registers;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242915
