Effects of elevated-temperature bias stressing on radiation response in power VDMOSFETs

Author

Stojadinovic, N. ; Djoric-Veljkovic, S. ; Manic, I. ; Davidovic, V. ; Golubovic, S.

Author_Institution

Fac. of Electron. Eng., Nis Univ., Yugoslavia

fYear

2001

fDate

2001

Firstpage

243

Lastpage

248

Abstract

The effects of pre-irradiation elevated-temperature bias stressing on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift in stressed devices and considerable mobility reduction in unstressed devices have been observed. The underlying changes of gate oxide-trapped charge and interface trap densities have been calculated and analysed in terms of the mechanisms responsible for pre-irradiation stress effects

Keywords

carrier mobility; dielectric thin films; electron traps; hole traps; interface states; power MOSFET; radiation effects; semiconductor device reliability; semiconductor device testing; thermal stresses; SiO₂-Si; elevated-temperature bias stressing; gate oxide-trapped charge; interface trap densities; irradiation induced threshold voltage shift; mobility reduction; power VDMOSFETs; pre-irradiation elevated-temperature bias stressing effects; pre-irradiation stress effects; radiation response; stressed devices; unstressed devices; Artificial satellites; Communication switching; Life testing; Orbits; Power engineering and energy; Power supplies; Power system reliability; Stress; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on the

Print_ISBN

0-7803-6675-1

Type

conf

DOI

10.1109/IPFA.2001.941495

Filename

941495