Title :
Clock tree synthesis for high performance ASICs
Author_Institution :
Motorola Inc., Chandler, AZ, USA
Abstract :
Using clock tree synthesis to create a high performance clocking network during layout requires the implementation of an active buffer distribution that is a design and technology specific trade-off between skew sensitivity, clock insertion delay, and simultaneously switching power dissipation
Keywords :
CMOS integrated circuits; application specific integrated circuits; circuit layout; clocks; digital integrated circuits; printed circuit design; PCB layout design; active buffer distribution; clock insertion delay; clock tree synthesis; design specific trade-off; high performance ASICs; high performance clocking network; layout; simultaneously switching power dissipation; skew sensitivity; technology specific trade-off; Application specific integrated circuits; CMOS technology; Clocks; Delay effects; Drives; Integrated circuit synthesis; Integrated circuit technology; Network synthesis; Pins; Wire;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242921
