Gate arrays simplify translation between high speed logic families

Author

Houghten, Jonathan L. ; Prioste, Jerry E.

Author_Institution

Motorola Inc., Chandler, AZ, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38139

Abstract

TTL dominates todays I/O specifications. However, ECL logic provides increased bandwidth and low noise in a transmission line environment. High performance designs increasingly need to combine ECL and TTL interfaces. This paper presents a flexible approach to mixed signal level translations (ECL/PECL and TTL) utilizing a single I/O cell on a family of ECL gate arrays. The incorporation of Schottky diodes within the bipolar process provides high performance on/off chip logic translations to complement the 2.6 Gb/s ECL I/O interface capability. Versatile high speed system applications are illustrated and described

Keywords

application specific integrated circuits; bipolar integrated circuits; digital integrated circuits; emitter-coupled logic; logic arrays; transistor-transistor logic; 2.6 Gbit/s; ASIC; ECL gate arrays; ECL logic; ETL gate arrays; I/O specifications; Schottky diodes; TTL; TTL/ECL translation; bandwidth; chip logic translations; interface capability; low noise; mixed signal level translations; on chip translation; single I/O cell; translation between high speed logic families; transmission line environment; Application specific integrated circuits; Bandwidth; Costs; Fabrication; Logic arrays; Logic design; Power supplies; Power transmission lines; Voltage; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242923

Filename

242923