DocumentCode :
3350772
Title :
A multi-chip module substrate testing algorithm
Author :
Yao, So-Zen ; Chou, Nan-Chi ; Cheng, Chung-Kuan ; Hu, T.C.
Author_Institution :
CSE Dept., California Univ., San Diego, La Jolla, CA, USA
fYear :
1991
fDate :
23-27 Sep 1991
Lastpage :
38078
Abstract :
Discusses substrate short/open fault detection in MCM manufacturing, and propose a complete open fault coverage algorithm which generates a minimum number of tests required to completely cover all open faults. The algorithm generates only about half of the test size compared to that of ordinary approaches. Multi-dimensional TSP algorithms are devised to optimize probe routes with quite encouraging results
Keywords :
combinatorial mathematics; fault location; integrated circuit testing; multichip modules; production testing; MCM manufacturing; TSP algorithms; fault detection; minimum number of tests; multi-chip module substrate; open fault coverage; optimize probe routes; test size; Capacitance; Circuit faults; Circuit testing; Fault detection; Logic testing; Manufacturing; Needles; Pins; Probes; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
Type :
conf
DOI :
10.1109/ASIC.1991.242925
Filename :
242925
Link To Document :
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