Functional block design using VHDL simulation and synthesis

Author

Weber, David M.

Author_Institution

Microelectron. Products Div., NCR, Colorado Springs, CO, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38108

Abstract

This is a case study comparison between traditional and VHDL design methods of a small sized logic module (1500 gates). The areas where design cycle improvements and gate count reductions were realized are discussed as well as VHDL development strategies undertaken to reduce the impact of the design tools´ limitations

Keywords

circuit layout CAD; large scale integration; specification languages; VHDL design methods; VHDL development strategies; case study; design cycle improvements; design tools´ limitations; gate count reductions; small sized logic module; traditional design methods; Circuit simulation; Clocks; Computational modeling; Design methodology; Libraries; Logic design; Logic gates; Microelectronics; Springs; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242929

Filename

242929

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3350829